Altera Quartus II Scripting - Manual (Page 513)

Chapter 3: Tcl Packages & Commands 3–383
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© July 2013 Altera Corporation Quartus II Scripting Reference Manual
create_timing_netlist
Usage
create_timing_netlist [-force_dat] [-grade <c|i|m|e|a>] [-model <fast|slow>]
[-no_latch] [-post_map] [-speed <speed>] [-temperature <value_in_C>] [-voltage
<value_in_mV>] [-zero_ic_delays] <operating_conditions>
Options
-force_dat: Option to force delay annotation
-grade <c|i|m|e|a>: Option to specify temperature grade
-model <fast|slow>: Option to specify timing model
-no_latch: Option to disable the analysis of latches as synchronous elements
-post_map: Option to perform timing analysis on the post-synthesis netlist
-speed <speed>: Speed grade
-temperature <value_in_C>: Operating temperature
-voltage <value_in_mV>: Operating voltage
-zero_ic_delays: Option to set all IC delays to zero
<operating_conditions>: Operating conditions Tcl object name string
Description
Creates the timing netlist by annotating the atom netlist with delay information using post-fitting results.
Use the -post_map option to obtain post-synthesis results.
The create_timing_netlist command skips delay annotation by default. Use -force_dat to rerun delay
annotation. This is required if any delay annotation setting is changed in the Quartus II project revision
(e.g. OUTPUT_PIN_LOAD).
Use "-model fast" to run the analysis using the fast corner delay models first. The -temperature, -voltage,
and -speed, options are also available. See help for set_operating_conditions for details on these options.
You can use model, temperature and voltage options to specify operating conditions while creating timing
netlist (temperature and voltage options are not supported by all families). You can also set operating
conditions by passing an operating conditions object name as a positional argument to
create_timing_netlist command. After timing netlist has been created, you can use
set_operating_conditions command to change timing models without deleting and re-creating the timing
netlist.
Use the -grade option to analyze the design at a different temperature grade. This option is provided to
support what-if analysis and is not recommended for final sign-off analysis.
Use the -no_latch option to analyze latches as combinational loops instead of synchronous elements.
Use the -zero_ic_delays option to set all IC delays in the netlist to zero.
Example
project_open my_top
# Create timing netlist before calling
# any report functions
create_timing_netlist
# Read SDC and update timing
read_sdc
update_timing_netlist