Document Outline

• Section III – Hardware Description
  • DOCUMENT ORGANIZATION
  • DOCUMENT HISTORY
  • CONTENTS
  • TABLES
  • FIGURES
  • ABBREVIATIONS
• 1 Overview
  • 1.1 Frame processing order
  • 1.2 Scope of this document
  • 1.3 Scope of Delivery
  • 1.4 Target FPGAs
  • 1.5 Designflow requirements
  • 1.6 Tested FPGA/Designflow combinations
  • 1.7 Release Notes
    • 1.7.1 Major differences between V2.4.x and V3.0.x
    • 1.7.2 Reading IP Core version from device
  • 1.8 Design flow
  • 1.9 OpenCore Plus Evaluation
  • 1.10 Simulation
• 2 Features and Registers
  • 2.1 Features
  • 2.2 Registers
  • 2.3 Extended ESC Features in User RAM
• 3 IP Core Installation
  • 3.1 Installation on Windows PCs
    • 3.1.1 System Requirements
    • 3.1.2 Installation
  • 3.2 Installation on Linux PCs
    • 3.2.1 System Requirements
    • 3.2.2 Installation
  • 3.3 Files located in the lib folder
  • 3.4 License File
  • 3.5 IP Core Vendor ID package
  • 3.6 Integrating the EtherCAT IP Core into the Altera Designflow
    • 3.6.1 Software Templates for example designs with NIOS processor
  • 3.7 EtherCAT Slave Information (ESI) / XML device description for example designs
• 4 IP Core Usage
  • 4.1 IP Catalog
  • 4.2 Qsys
• 5 IP Core Configuration
  • 5.1 Documentation
  • 5.2 Parameters
    • 5.2.1 Product ID tab
    • 5.2.2 Physical Layer tab
    • 5.2.3 Internal Functions tab
    • 5.2.4 Feature Details tab
    • 5.2.5 Process Data Interface tab
      • 5.2.5.1 No Interface and General Purpose I/O
      • 5.2.5.2 Digital I/O Configuration
      • 5.2.5.3 µController Configuration (8/16Bit)
      • 5.2.5.4 SPI Configuration
      • 5.2.5.5 Avalon Configuration
      • 5.2.5.6 AXI3 Configuration
• 6 Example Designs
  • 6.1 EBV Cyclone III DBC3C40 with Digital I/O
    • 6.1.1 Configuration and resource consumption
    • 6.1.2 Functionality
    • 6.1.3 Implementation
    • 6.1.4 SII EEPROM
    • 6.1.5 Downloadable configuration file
  • 6.2 EBV Cyclone IV DBC4CE55 with NIOS
    • 6.2.1 Configuration and resource consumption
    • 6.2.2 Functionality
    • 6.2.3 Implementation
    • 6.2.4 SII EEPROM
    • 6.2.5 Downloadable configuration file
  • 6.3 Altera Cyclone IV DE2-115 with NIOS and MII
    • 6.3.1 Configuration and resource consumption
    • 6.3.2 Functionality
    • 6.3.3 Implementation
    • 6.3.4 SII EEPROM
    • 6.3.5 Downloadable configuration file
  • 6.4 Altera Cyclone IV DE2-115 with NIOS and RGMII
    • 6.4.1 Configuration and resource consumption
    • 6.4.2 Functionality
    • 6.4.3 Downloadable configuration file
• 7 FPGA Resource Consumption
• 8 IP Core Signals
  • 8.1 General Signals
    • 8.1.1 Clock source example schematics
  • 8.2 SII EEPROM Interface Signals
  • 8.3 LED Signals
  • 8.4 Distributed Clocks SYNC/LATCH Signals
  • 8.5 Physical Layer Interface
    • 8.5.1 MII Interface
    • 8.5.2 RMII Interface
    • 8.5.3 RGMII Interface
  • 8.6 PDI Signals
    • 8.6.1 General PDI Signals
    • 8.6.2 Digital I/O Interface
    • 8.6.3 SPI Slave Interface
    • 8.6.4 Asynchronous 8/16 Bit µController Interface
      • 8.6.4.1 8 Bit µController Interface
      • 8.6.4.2 16 Bit µController Interface
    • 8.6.5 Avalon On-Chip Bus
    • 8.6.6 AXI3 On-Chip Bus
• 9 Ethernet Interface
  • 9.1 PHY Management interface
    • 9.1.1 PHY Management Interface Signals
    • 9.1.2 PHY Address Configuration
    • 9.1.3 Separate external MII management interfaces
    • 9.1.4 MII management timing specifications
  • 9.2 MII Interface
    • 9.2.1 MII Interface Signals
    • 9.2.2 TX Shift Compensation
    • 9.2.3 MII Timing specifications
    • 9.2.4 MII example schematic
  • 9.3 RMII Interface
    • 9.3.1 RMII Interface Signals
    • 9.3.2 RMII example schematic
  • 9.4 RGMII Interface
    • 9.4.1 RGMII Interface Signals
    • 9.4.2 RGMII example schematic
    • 9.4.3 RGMII RX timing options
      • 9.4.3.1 RX_CLK Delay in PHY
      • 9.4.3.2 RX_CLK Delay on PCB
      • 9.4.3.3 RX_CLK Delay in FPGA with PLL
      • 9.4.3.4 RX_CLK Delay in FPGA without PLL
    • 9.4.4 RGMII TX timing options
      • 9.4.4.1 TX_CLK Delay in PHY
      • 9.4.4.2 TX_CLK Delay on PCB
      • 9.4.4.3 TX_CLK Delay in FPGA with PLL
      • 9.4.4.4 TX_CLK Delay in FPGA without PLL
• 10 PDI Description
  • 10.1 Digital I/O Interface
    • 10.1.1 Interface
    • 10.1.2 Configuration
    • 10.1.3 Digital Inputs
    • 10.1.4 Digital Outputs
    • 10.1.5 Output Enable
    • 10.1.6 SyncManager Watchdog
    • 10.1.7 SOF
    • 10.1.8 OUTVALID
    • 10.1.9 Timing specifications
  • 10.2 SPI Slave Interface
    • 10.2.1 Interface
    • 10.2.2 Configuration
    • 10.2.3 SPI access
    • 10.2.4 Address modes
    • 10.2.5 Commands
    • 10.2.6 Interrupt request register (AL Event register)
    • 10.2.7 Write access
    • 10.2.8 Read access
      • 10.2.8.1 Read Wait State
      • 10.2.8.2 Read Termination
    • 10.2.9 SPI access errors and SPI status flag
    • 10.2.10 2 Byte and 4 Byte SPI Masters
    • 10.2.11 Timing specifications
  • 10.3 Asynchronous 8/16 bit µController Interface
    • 10.3.1 Interface
    • 10.3.2 Configuration
    • 10.3.3 µController access
    • 10.3.4 Write access
    • 10.3.5 Read access
    • 10.3.6 µController access errors
    • 10.3.7 Connection with 16 bit µControllers without byte addressing
    • 10.3.8 Connection with 8 bit µControllers
    • 10.3.9 Timing Specification
  • 10.4 Avalon Slave Interface
    • 10.4.1 Interface
    • 10.4.2 Configuration
    • 10.4.3 Interrupts
    • 10.4.4 Data Bus With and SyncManager Configuration
    • 10.4.5 Timing specifications
  • 10.5 AXI3 On-Chip Bus
    • 10.5.1 Interface
    • 10.5.2 Configuration
    • 10.5.3 Interrupts
    • 10.5.4 Timing specifications
• 11 Distributed Clocks SYNC/LATCH Signals
  • 11.1 Signals
  • 11.2 Timing specifications
• 12 SII EEPROM Interface (I²C)
  • 12.1 Signals
  • 12.2 EEPROM Emulation
  • 12.3 Timing specifications
• 13 Electrical Specifications
• 14 Synthesis Constraints
• 15 Appendix
  • 15.1 Support and Service
    • 15.1.1 Beckhoff’s branch offices and representatives
  • 15.2 Beckhoff Headquarters