Prom decoder, sram and dma control register, Prom decoder, sram and dma control register -54 – Motorola MVME172 User Manual
Page 132
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VMEchip2
2
PROM Decoder, SRAM and DMA Control Register
This register controls the snoop control bits used by the DMAC when it is
accessing table entries.
SRAMS
These VMEchip2 bits are not used on the MVME172.
TBLSC
These bits control the snoop signal lines on the local bus
when the DMAC is table walking.
0
Snoop inhibited
1
Snoop enabled
ROM0
This VMEchip2 bit is not used on the MVME172. Its
function is performed by the ROM0 bit in the PROM
Access Time Control Register in the MC2 chip. Refer to
Chapter 3.
WAIT RMW This function is not used on the MVME172.
ADR/SIZ
$FFF40030 (8 bits [6 used] of 32)
BIT
23
22
21
20
19
18
17
16
NAME
WAIT RMW
ROM0
TBLSC
SRAMS
OPER
R/W
R/W
R/W
R/W
RESET
0 PSL
1 PSL
0 PS
0 PS
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