Motorola MVME172 - Manual (Page 74)

1-56 Computer Group Literature Center Web Site
Board Description and Memory Maps
1
SCSI Parity Error
Note The 400/500-Series MVME172 models do not contain parity
DRAM.
Description:
Parity error detected while the 53C710 was reading DRAM.
MPU Notification:
53C710 Interrupt.
Status:
53C710 DMA Status Register 53C710 DMA Interrupt Status Register
MC2 chip SCSI Error Status Register ($FFF4202C).
Comments:
53C710 interrupt enables are controlled in the 53C710 and in the MC2
chip SCSI Interrupt Control Register ($FFF4202F).
SCSI Off-Board Error
Description:
Error encountered while the 53C710 was attempting to go to the VMEbus.
MPU Notification:
53C710 Interrupt.
Status:
53C710 DMA Status Register 53C710 DMA Interrupt Status Register
MC2 chip SCSI Error Status Register ($FFF4202C).
Comments:
53C710 interrupt enables are controlled in the 53C710 and in the MC2
chip SCSI Interrupt Control Register ($FFF4202F).
SCSI LTO Error
Description:
Local Bus Time-out occurred while the 53C710 was local bus master.