Motorola MVME172 - Manual (Page 192)

3-4 Computer Group Literature Center Web Site
MC2 Chip
3
MPU Channel Attention access is used to cause the 82596CA to begin
executing memory resident Command blocks. To execute an MPU
Channel Attention, the MC68060-bus master performs a simple read or
write to address $FFF46004.
MC68060-Bus Master Support for 82596CA
The 82596CA has DMA capability with an Intel i486-bus interface. When
it is the local bus master, external hardware is needed to convert its bus
cycles into MC68060-bus cycles. When the 82596CA has local bus
mastership, the MC2 chip drives the following MC68060 signal lines:
❏ Snoop Control SC1-SC0 (with the value programmed into the LAN
Interrupt Control Register).
❏ Transfer Types TT1-TT0 (with the value of %00).
❏ Transfer Modifiers TM2-TM0 (with the value of %101).
❏ Transfer Start
❏ Read
❏ Size
❏ Transfer in progress
LANC Bus Error
The 82596CA does not provide a way to terminate a bus cycle with an
error indication. Bus error are processed in the following way. The
82596CA interface logic monitors all bus cycles initiated by the 82596CA,
and if a bus error is indicated (TAE* = 0 and TA* =1), the Back Off signal
(BOFF*) to the 82596CA is asserted to keep the 82596CA off the local bus
and prevent it from transmitting bad data or corrupting local memory. The
LANC Error Status Register in the MC2 chip is updated and a LANC bus
error interrupt is generated if it is enabled in the MC2 chip. The Back Off
signal remains asserted until the 82596CA is reset via a port reset
command. After the 82596CA is reset, pending operations must be
restarted.