Motorola MVME172 - Manual (Page 326)

5-36 Computer Group Literature Center Web Site
MCECC
5
clock, unless they are already slowed by NCEBEN being
set. FSTRD is cleared by Power-up or Local Reset if the
FSTRD bit in the reset serial bit stream is 0. It is set by
Power-up, soft, or Local Reset if the FSTRD bit in the
reset serial bit stream is 1. Note that this bit can also be
read in the Memory Configuration Register.
STATCOL When the STATCOL bit is set, the RACODE and/or
RADATA bits in the Scrub Control Register can be set.
When it is cleared, they cannot. STATCOL is initialized
by Power-up, soft, or Local Reset to match the value of
the STATCOL bit in the reset serial bit stream.
WRHDIS This bit controls a function that is not currently used in the
MCECC.
Defaults Register 2
It is not recommended that non-test software write to this register.
RESST2-RESST0
These general purpose read/write bits are initialized by
power-up, soft, or local reset, to match the RESST2-
RESST0 bits from the reset serial bit stream.
NOCACHE
When NOCACHE is cleared, the HITDIS bit in the Scrub
Control Register can be cleared by software. When it is
set, the HITDIS bit cannot be cleared. NOCACHE is
ADR/SIZ 1st $FFF43078/2nd $FFF43178 (8-bits)
BIT 31 30 29 28 27 26 25 24
NAME FRC_OPEN XY_FLIP REFDIS TVECT NOCACHE RESST2 RESST1 RESST0
OPER R/W R/W R/W R/W R/W R/W R/W R/W
RESET 0 PLS 0 PLS 0 PLS V PLS V PLS V PLS V PLS V PLS