Motorola MVME172 - Manual (Page 19)

1-1
1
1 Board Description
and Memory Maps
Introduction
This manual provides programming information for the MVME172
Embedded Controller. Extensive programming information is provided for
the Application-Specific Integrated Circuit (ASIC) devices used on the
board. Reference information is included for the Large Scale Integration
(LSI) devices used on the board and sources for additional information are
provided.
This chapter briefly describes the board level hardware features of the
MVME172 Embedded Controller. The chapter begins with a board level
overview and features list. Memory maps are next, and the chapter closes
with some general software considerations such as cache coherency,
interrupts, and bus errors.
All programmable registers in the MVME172 that reside in ASICs are
covered in the chapters on those ASICs. Chapter 2 covers the VMEchip2,
Chapter 3 covers the MC2 chip, and Chapter 4 covers the IP2 chip. Chapter
5 covers the MCECC chip, used only on 200/300-Series MVME172.
Appendix A describes using interrupts. For those interested in
programmable register bit definitions and less interested in hardware
functionality, focus on Chapters 2, 3, 4, and 5. In some cases, however,
Chapter 1 gives related background information.
Overview
The MVME172 is based on the MC68060 or MC68LC060
microprocessor. The MVME172 is available in various versions with the
features listed in
Table 1-1 on page 1-3 . A “No VMEbus” option is also
available.
The I/O connection for the 200/300-Series MVME172 is provided through
four RJ-45 front panel connectors.