Motorola MVME172 - Manual (Page 27)

Memory Maps
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1
VMEbus Interface and VMEchip2
The local bus to VMEbus interface and the VMEbus to local bus interface
are provided by the VMEchip2. The VMEchip2 can also provide the
VMEbus system controller functions. Refer to the VMEchip2 in Chapter 2
for detailed programming information.
Note that the ABORT switch logic in the VMEchip2 is not used. The GPI
inputs to the VMEchip2 which are located at $FFF40088 bits 7-0 are not
used. The
ABORT switch interrupt is integrated into the
MC2 chip ASIC at location $FFF42043. The GPI inputs are integrated into
the MC2 chip ASIC at location $FFF4202C bits 23-16.
Memory Maps
There are two points of view for memory maps: 1) the mapping of all
resources as viewed by local bus masters (local bus memory map), and 2)
the mapping of onboard resources as viewed by VMEbus masters
(VMEbus memory map).
The memory and I/O maps which are described in the following tables are
correct for all local bus masters. There is some address translation
capability in the VMEchip2. This allows multiple MVME172 modules on
the same VMEbus with different virtual local bus maps as viewed by
different VMEbus masters.
Local Bus Memory Map
The local bus memory map is split into different address spaces by the
transfer type (TT) signals. The local resources respond to the normal
access and interrupt acknowledge codes.
Normal Address Range
The memory map of devices that respond to the normal address range is
shown in the following tables. The normal address range is defined by the
Transfer Type (TT) signals on the local bus. On the MVME172, Transfer
Types 0, 1, and 2 define the normal address range. Table 1-2 is the entire