Motorola MVME172 - Manual (Page 86)

2-8 Computer Group Literature Center Web Site
VMEchip2
2
The requester requests the bus if any of the following conditions occur:
1. The local bus master initiates either a data transfer cycle or an
interrupt acknowledge cycle to the VMEbus.
2. The chip is requested to acquire control of the VMEbus as signaled
by the DWB input signal pin.
3. The chip is requested to acquire control of the VMEbus as signaled
by the DWB control bit in the LCSR.
The local bus to VMEbus requester in the VMEchip2 implements a fair
mode. By setting the LVFAIR bit, the requester refrains from requesting
the VMEbus until it detects its assigned request line in its negated state.
The local bus to VMEbus requester attempts to release the VMEbus when
the requested data transfer operation is complete, the DWB pin is negated,
the DWB bit in the LCSR is negated and the bus is not being held by a lock
cycle. The requester releases the bus as follows:
1. When the chip is configured in the release-when-done (RWD)
mode, the requester releases the bus when the above conditions are
satisfied.
2. When the chip is configured in the release-on-request (ROR) mode,
the requester releases the bus when the above conditions are
satisfied and there is a bus request pending on one of the VMEbus
request lines.
To minimize the timing overhead of the arbitration process, the local bus
to VMEbus requester in the VMEchip2 executes an early release of the
VMEbus. If it is about to release the bus and it is executing a VMEbus
cycle, the requester releases BBSY before its associated master completes
the cycle. This allows the arbiter to arbitrate any pending requests, and
grant the bus to the next requester, at the same time that the active master
completes its cycle.