Motorola MVME172 - Manual (Page 324)

5-34 Computer Group Literature Center Web Site
MCECC
5
Error Syndrome Register
S7-S0 SYNDROME7-0 reflects the syndrome value at the last
logging of an error. The eight bit code indicates the
position of the data error. When all the bits are zero, there
is no error. Note that if the logged error was non-
correctable, then these bits are meaningless. Refer to the
section on Syndrome Decode.
Defaults Register 1
It is not recommended that non-test software write to this register.
RSIZ2-RSIZ0
RSIZ2-RSIZ0 determine the size of the DRAM array that
is assumed by the MCECC. They control the size as
follows:
ADR/SIZ 1st $FFF43070/2nd $FFF43170 (16-bits)
BIT 31 30 29 28 27 26 25 24
NAME S7 S6 S5 S4 S3 S2 S1 S0
OPER R R R R R R R R
RESET 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS
ADR/SIZ 1st $FFF43074/2nd $FFF43174 (8-bits)
BIT 31 30 29 28 27 26 25 24
NAME WRHDIS STATCOL FSTRD SELI1 SELI0 RSIZ2 RSIZ1 RSIZ0
OPER R/W R/W R/W R/W R/W R/W R/W R/W
RESET 0 PL V PLS V PLS V PLS V PLS V PLS V PLS V PLS