Motorola MVME172 - Manual (Page 299)

Programming Model
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stream". The reset serial bit stream initializes the MCECC pair by setting
or resetting the bits that appear in the Defaults 1 and Defaults 2 Registers.
Software can override this initial setting by writing to the Defaults
Registers. It is not recommended that non-test software alter the bits in the
Defaults Registers.
Programming Model
This section defines the programming model for the control and status
registers (CSRs) in the MCECC pair. The base address of the CSRs is hard
coded to the address $FFF43000 for the MCECC pair on the first
mezzanine board and $FFF43100 for the MCECC pair on the second
mezzanine board. The CSRs for the two MCECCs appear at the same
address, (one on D16-D31, the other on D00-D15). Hardware
automatically duplicates the values that are written to the CSRs in the
upper MCECC (the one that connects to D16-D31) to the lower MCECC
(the one that connects to D0-D15). Hence Software only needs to write to
the control registers in the upper MCECC. This duplicating function can
be disabled by software for test purposes.
Some effort has gone into making the register map for the first eight
registers, of the MCECC pair, look as close as possible to that for the eight
registers contained in the MEMC040, the parity memory controller used in
the MVME167 and MVME187. Where there are differences, they are
noted. The remaining 18 registers contain functions unique to the MCECC
pair.
The possible operations for each bit in the CSR are as follows:
R This bit is a read only status bit.
R/W This bit is readable and writable.
R/C This status bit is cleared by writing a one to it.
C Writing a zero to this bit clears this bit or another bit.
This bit reads zero.
S Writing a one to this bit sets this bit or another bit.
This bit reads zero.