Motorola MVME172 - Manual (Page 29)

Memory Maps
http://www.mcg.mot.com/literature 1-11
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Notes 1. Devices mapped at $FFF80000-$FFF9FFFF also appear at
$00000000- $001FFFFF when the ROM0 bit in the MC2
chip EPROM control register is high (ROM0=1). ROM0 is
set to 1 after each reset. The ROM0 bit must be cleared before
other resources (DRAM or SRAM) can be mapped in this
range ($00000000 - $001FFFFF).
The EPROM/Flash memory map is also controlled by the
EPROM size and by control bit V11 in the MC2 chip ASIC.
Refer to the EPROM/Flash configuration tables in your
MVME172 installation manual for further details.
2. This area is user-programmable. The DRAM and SRAM
decoder is programmed in the MC2 chip, the local-to-
VMEbus decoders are programmed in the VMEchip2, and
the IP memory space is programmed in the IP2.
3. Size is approximate.
4. Cache inhibit depends on the devices in the area mapped.
5. The EPROM and Flash are dynamically sized by the MC2
chip ASIC from an 8-bit private bus to the 32-bit MPU local
bus.
6. These areas are not decoded unless one of the
programmable decoders is initialized to decode this space. If
they are not decoded and the local timer is enabled, an access
to this address range will generate a local bus time-out.