Motorola MVME172 - Manual (Page 241)

Functional Description
http://www.mcg.mot.com/literature 4-5
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Clocking Environments and Performance
The IP2 chip has two clock domains. The majority of the logic is controlled
by the MC68060 local bus clock which can be 25 MHz or 32 MHz. The
IndustryPack interface is controlled by the IndustryPack clock. The
IndustryPack clock can be 8 MHz or set equal to the local bus clock. When
logic signals cross from one clock domain to another, they must be
synchronized to the new clock frequency. The latency time due this
synchronization is generally hidden due to the FIFOs in the data path.
However, there are two functions where the latency time affects
performance. One of them is when a local bus master such at the MC68060
accesses an IndustryPack resource, such as reading back to back memory
locations. One to two IP clock cycles of overhead is associated with this
function. The other is when arbitration logic must resolve inputs from both
clock domains to determine which IndustryPack will be granted DMA
service. There are two IP clock cycles of overhead associated with this
function. The following table explains the effect of this latency for given
clocking environments.
The bandwidth which is specified in the following table is the available
bandwidth to the IndustryPack bus. This bandwidth can be split between
one, two, three, or four IP modules.