Motorola MVME172 - Manual (Page 292)

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MCECC
5
Functional Description
The following sections provide an overview of the functions provided by
the MCECC. A detailed programming model for the MCECC control and
status registers is provided in the Programming Model section.
General Description
The MCECC is designed to be used as a set of two chips. A pair of
MCECCs works with x4 DRAM memory chips to form a memory system
for the MVME172 boards. A pair of MCECCs that is connected to
implement a memory control function is referred to as an "MCECC pair".
The MCECC pair provides all the functions required to implement a
memory system. These include programmable map decoding, memory
control, refresh, and a scrubber. The scrubber, when it is enabled,
periodically scans memory looking for errors. If the scrubber finds a single
bit error in the memory array, it corrects it. This prevents soft single bit
errors from becoming double bit errors.
Performance
The MCECC pair is specifically designed to provide maximum
performance for cache line (burst) cycles to and from the MC68060 bus.
This is done by providing a four-way interleave between the 32-bit
MC68060 data bus and the 128 bit (144 with check bits) DRAM. This
permits burst accesses to be pipelined, giving high performance from
standard speed, static column, DRAMs. For example, burst reads can be
sustained at speeds of 7 clocks per line of four four-bytes (8 clocks per line
with BERR enabled or FSTRD cleared). If the local MC68060 bus clock
frequency is 25MHz, this gives an average access time of 70ns (80ns with
BERR or no FSTRD) per four-byte. Burst writes can be sustained at 5
clocks per line, for an average of 50 ns at 33 MHz.
Random (non-burst) reads and writes are pipelined to the extent possible.
Random reads take four clocks (five clocks with BERR on or FSTRD
cleared).