Motorola MVME172 - Manual (Page 328)

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MCECC
5
operating at 25 MHz. This sequence may have to be altered to perform the
scrub more slowly if the scrub causes the DRAM to consume too much
power at full speed.
1. Make sure that the scrubber is disabled by clearing the SCRBEN bit
in the Scrub Control Register. (Clear bit 27 of offset $24.)
2. Make sure that the scrubber is done with any old scrub cycles by
waiting for the SCRB bit in the Scrub Control Register to be cleared.
(Wait for bit 28 of offset $24 = 0.)
3. Discontinue all accesses from the MC68060 bus to the DRAM.
4. Ensure that all accesses have stopped by clearing the RAMEN bit in
the DRAM Control Register. (Clear bit 0 of offset $18)
5. Set the ZFILL bit in the MCECC pair. (Set Bit 28 of offset $20)
6. Set the Scrub Time On/Time Off Register for the maximum rate and
to do write cycles, by setting the SRDIS bit, setting all of the STON
bits, and clearing all of the STOFF bits. (Write $B8 to offset $34)
7. Enable scrubbing by setting the SCRBEN bit in the Scrub Control
Register. (Set bit 27 of offset $24.)
8. Ensure that the zero-fill has started by waiting for the SCRB bit in
the Scrub Control Register to be set. (Wait for bit 28 of offset $24 =
1.)
9. Ensure that the zero-fill stops after one time through, by clearing the
SCRBEN bit in the Scrub Control Register. (Clear bit 27 of offset
$24.)
10. Wait for the zero-fill to complete by waiting for the SCRB bit in the
Scrub Control Register to be cleared. (Wait for bit 28 of offset $24
= 0.)
11. Clear the ZFILL bit in the MCECC pair. (Clear Bit 28 of offset $20)
12. The entire DRAM that is controlled by this MCECC is now zero-
filled. The software can now program the appropriate scrubbing
mode and other desired initialization, and enable DRAM for
operation.