Motorola MVME172 - Manual (Page 140)

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VMEchip2
2
This register controls the VMEbus interrupter.
IRQL These bits define the level of the VMEbus interrupt
generated by the VMEchip2. A VMEbus interrupt is
generated by writing the desired level to these bits. These
bits always read 0 and writing 0 to these bits has no effect.
IRQS This bit is the IRQ status bit. When this bit is high, the
VMEbus interrupt has not been acknowledged. When this
bit is low, the VMEbus interrupt has been acknowledged.
This is a read-only status bit.
IRQC This bit is VMEbus interrupt clear bit. When this bit is set
high, the VMEbus interrupt is removed. This feature is
only used when the IRQ1 broadcast mode is used. Normal
VMEbus interrupts should never be cleared. This bit
always reads 0 and writing a 0 to this bit has no effect.
IRQ1S These bits control the function of the IRQ1 signal line on
the VMEbus:
0 The IRQ1 signal from the interrupter is
connected to the IRQ1 signal line on the
VMEbus.
1 The output from tick timer 1 is connected to
the IRQ1 signal line on the VMEbus.
2 The IRQ1 signal from the interrupter is
connected to the IRQ1 signal line on the
VMEbus.
3 The output from tick timer 2 is connected to
the IRQ1 signal line on the VMEbus.