Motorola MVME172 - Manual (Page 210)

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MC2 Chip
3
DRAM Parity Error Interrupt Control Register
The DRAM Parity Error Interrupt Control Register controls the interrupt
logic for parity error interrupts. In the MVME172, the parity control and
interrupt logic is contained in the DRAM Parity Error Interrupt Control
Register and the DRAM Control Register located at $FFF4201C and
$FFF42048 respectively.
IL2-IL0 These three bits select the interrupt level for the DRAM
parity error detection. Level 0 does not generate an
interrupt.
ICLR Writing a logic 1 to this bit clears the DRAM parity error
detection interrupt. This clears the INT bit in this register.
This bit is always read as zero.
IEN This bit set to a one enables the parity error interrupt. If
this bit is set to a one, and the PAREN and PARINT bits
are set to 01 or 11, and a parity error occurs, an interrupt
is generated at the level programmed in the IL2-IL0 bits.
The PAREN and PARINT bits are located at $FFF42048
at bit 26 and 25.
INT When this bit is high, a interrupt is being generated due to
a DRAM parity error. The interrupt is at the level
programmed in IL2-IL0.
ADR/SIZ $FFF4201C (8 bits)
BIT 31 30 29 28 27 26 25 24
NAME INT IEN ICLR IL2 IL1 IL0
OPER R R R R/W C R/W R/W R/W
RESET 0 0 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL