Motorola MVME172 - Manual (Page 72)

1-54 Computer Group Literature Center Web Site
Board Description and Memory Maps
1
Comments:
This indicates the DMAC attempted to access a local bus address at which
there was no resource. If the TBL bit is set (address $FFF40048 bit 2) the
error occurred during a command table access, otherwise the error
occurred during a data access.
DMAC TEA - Cause Unidentified
Description:
An error occurred while the DMAC was local bus master and additional
status was not provided.
MPU Notification:
DMAC interrupt (when enabled).
Status:
The DLBE bit is set in the DMAC Status Register (address $FFF40048 bit
6).
Comments:
An 8- or 16-bit write to the LCSR in the VMEchip2 causes this error. If the
TBL bit is set (address $FFF40048 bit 2) the error occurred during a
command table access, otherwise the error occurred during a data access.
LAN Parity Error
Note The 400/500-Series MVME172 models do not contain parity
DRAM.
Description:
Parity error while the LANCE was reading DRAM MPU.
Notification:
MC2 chip Interrupt (LAN ERROR IRQ).
Status:
MC2 chip LAN Error Status Register ($FFF42028).