Motorola MVME172 - Manual (Page 67)

Software Support Considerations
http://www.mcg.mot.com/literature 1-49
1
VMEbus Access Time-out
A VMEbus Access Time-out occurs whenever a VMEbus bound transfer
does not receive a VMEbus bus grant within the programmed time. This is
usually caused by another bus master holding the bus for an excessive
period of time.
VMEbus BERR*
A VMEbus BERR* occurs when the BERR* signal line is asserted on the
VMEbus while a local bus master is accessing the VMEbus. VMEbus
BERR* should occur only if: an initialization routine samples to see if a
device is present on the VMEbus and it is not, software accesses a
nonexistent device within the VMEbus range, incorrect configuration
information causes the VMEchip2 to incorrectly access a device on the
VMEbus (such as driving LWORD* low to a 16-bit board), a hardware
error occurs on the VMEbus, or a VMEbus slave reports an access error
(such as parity error).
Local DRAM Parity Error
Note The 400/500-Series MVME172 models do not contain parity
DRAM.
When parity checking is enabled, the current bus master receives a bus
error if it is accessing the local DRAM and a parity error occurs.
VMEchip2
An 8- or 16-bit write to the LCSR in the VMEchip2 causes a local BERR*.
Bus Error Processing
Because different conditions can cause bus error exceptions, the software
must be able to distinguish the source. To aid in this, status registers are
provided for every local bus master. The next section describes the various
causes of bus error and the associated status registers.