Motorola MVME172 - Manual (Page 92)

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VMEchip2
2
The DMAC requester requests the bus as required to transfer data to or
from the FIFO buffer.
The requester implements a fair mode. By setting the DFAIR bit, the
requester refrains from requesting the bus until it detects its assigned
request line in its negated state.
The requester releases the bus when requested to by the DMA controller.
The DMAC always releases the VMEbus when the FIFO is full (VMEbus
to local bus) or empty (local bus to VMEbus). The DMAC can also be
programmed to release the VMEbus when another VMEbus master
requests the bus, when the time on timer has expired, or when the time on
timer has expired and another VMEbus master is requesting the bus. To
minimize the timing overhead of the arbitration process, the DMAC
requester executes an early release of the bus. If it is about to release the
bus and it is executing a VMEbus cycle, the requester releases BBSY
before its associated VMEbus master completes the cycle. This allows the
arbiter to arbitrate any pending requests, and grant the bus to the next
requester, at the same time that the DMAC completes its cycle.
Tick and Watchdog Timers
The VMEchip2 has two 32-bit tick timers and a watchdog timer. The tick
timers run on a 1 MHz clock which is derived from the local bus clock by
the prescaler.
Prescaler
The prescaler is used to derive the various clocks required by the tick
timers, VME access timers, reset timer, bus arbitration timer, local bus
timer, and VMEbus timer. The prescaler divides the local bus clock to
produce the constant-frequency clocks required. Software is required to
load the appropriate constant, depending upon the local bus clock,
following reset to ensure proper operation of the prescaler.