Motorola MVME172 User Manual
Page 280
4-44
Computer Group Literature Center Web Site
IP2 Chip
4
Programmable Clock General Control Register
PS2-0
These three bits select the frequency of the pre-scale logic
output The MC68060 bus clock (BCK) is used as the input
to the pre-scale logic. BCK is ether 25 MHz or 32 MHz.
BCK frequency can be determined by examining the
Version Register in the MC2 chip ASIC.
CLR
Setting this bit forces the programmable clock’s internal
registers (except for the interrupt and general control
registers) to zero. These registers include the pre-scaler
and timer counters. Note that these registers will remain
cleared until the CLR bit is set to a zero.
EN
When the EN bit is set, the programmable clock is
enabled. When it is cleared, the programmable clock is
suspended. EN performs its function by
ADR/SIZ
$FFFBC081 (8 bits)
BIT
7
6
5
4
3
2
1
0
NAME
PLTY
PLS
0
EN
CLR
PS2
PS1
PS0
OPER
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
RESET
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
PS2-PS0
Pre-scaler Output Frequency
PLS = 0
PLS = 1
0
BCK/2
No Output
1
BCK/4
BCK/2
2
BCK/8
BCK/4
3
BCK/16
BCK/8
4
BCK/32
BCK/16
5
BCK/64
BCK/32
6
BCK/128
BCK/64
7
BCK/256
BCK/128