Motorola MVME172 - Manual (Page 260)

4-24 Computer Group Literature Center Web Site
IP2 Chip
4
PLTY When this bit is low, interrupt is activated by a falling
edge/low level of the IndustryPack IRQ*. When this bit is
high, interrupt is activated by a rising edge/high level of
the IndustryPack IRQ*. Note that if this bit is changed
while the E/L* bit is set (or is being set), an interrupt may
be generated. This can be avoided by setting the ICLR bit
during write cycles that change the PLTY bit. Because
IndustryPack IRQ*s are active low, PLTY would
normally be cleared.
IP_a, IP_b, IP_c, and IP_d; General Control Registers
The registers which control IP_c and IP_d are not used on the 200/300-
Series MVME172.
MEN a_MEN/b_MEN/c_MEN/d_ MEN enable the local bus to
perform read/write accesses to their corresponding
IndustryPack memory space when set, and disable such
accesses when cleared. When a double size IndustryPack
is used in ab, a_MEN should be set and the WIDTH and
MEN control bits in the IP_b General Control Register
should be cleared. When a double size IndustryPack is
used in cd, c_MEN should be set, and the WIDTH and
MEN control bits in the IP_d General Control Register
should be cleared.
ADR/SIZ $FFFBC018 through $FFFBC01B (8 bits each)
BIT 7 6 5 4 3 2 1 0
NAME($18) a_ERR 0 a_RT1 a_RT0 a_WIDTH1 a_WIDTH0 a_BTD a_MEN
NAME($19) b_ERR 0 b_RT1 b_RT0 b_WIDTH1 b_WIDTH0 b_BTD b_MEN
NAME($1A) c_ERR 0 c_RT1 c_RT0 c_WIDTH1 c_WIDTH0 c_BTD0 c_MEN
NAME($1B) d_ERR 0 d_RT1 d_RT0 d_WIDTH1 d_WIDTH0 d_BTD d_MEN6
OPER R R/W R/W R/W R/W R/W R/W R/W
RESET ? R 0 R 0 R 0 R 0 R 0 R 1 R 0 R