Motorola MVME172 - Manual (Page 16)

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FIGURES
Figure 1-1. 200/300-Series MVME172 Block Diagram ........................................... 1-6
Figure 1-2. 400/500-Series MVME172 Block Diagram ........................................... 1-7
Figure 2-1. VMEchip2 Block Diagram ..................................................................... 2-5
TABLES
Table 1-1. MVME172 Features Summary................................................................. 1-3
Table 1-2. Redundant Functions in the VMEchip2 and MC2 Chip ......................... 1-8
Table 1-3. 200/300-Series MVME172 Local Bus Memory Map ............................ 1-10
Table 1-4. 400/500-Series MVME172 Local Bus Memory Map ............................ 1-12
Table 1-5. 200/300-Series MVME172 Local I/O Devices Memory Map ............... 1-14
Table 1-6. 400/500-Series MVME172 Local I/O Devices Memory Map ............... 1-18
Table 1-7. VMEchip2 Memory Map (Sheet 1 of 3) ................................................ 1-22
Table 1-8. MC2 Chip Register Map ........................................................................ 1-27
Table 1-9. IP2 Chip Overall Memory Map.............................................................. 1-28
Table 1-10. IP2 Chip Memory Map - Control and Status Registers ....................... 1-29
Table 1-11. MCECC Internal Register Memory Map ............................................ 1-35
Table 1-12. Z85230 SCC Register Addresses ......................................................... 1-37
Table 1-13. 82596CA Ethernet LAN Memory Map................................................ 1-38
Table 1-14. 53C710 SCSI Memory Map ............................................................... 1-39
Table 1-15. MK48T58 BBRAM/TOD Clock Memory Map ................................... 1-40
Table 1-16. BBRAM Configuration Area Memory Map ....................................... 1-41
Table 1-17. TOD Clock Memory Map .................................................................... 1-42
Table 2-1. VMEchip2 Memory Map - LCSR Summary (Sheet 1 of 2) .................. 2-22
Table 2-2. DMAC Command Table Format ............................................................ 2-53
Table 2-3. Local Bus Interrupter Summary ............................................................ 2-76
Table 2-4. VMEchip2 Memory Map (GCSR Summary) ...................................... 2-104
Table 3-1. DRAM Performance................................................................................. 3-6
Table 3-2. MC2 Chip Register Map ......................................................................... 3-9
Table 3-3. Interrupt Vector Base Register Encoding and Priority ........................... 3-14
Table 3-4. DRAM Size Control Bit Encoding......................................................... 3-27
Table 3-5. DRAM Size Control Bit Encoding......................................................... 3-28
Table 3-6. SRAM Size Control Bit Encoding ......................................................... 3-28
Table 3-7. SRAM Size Control Bit Encoding ......................................................... 3-29
Table 4-1. IP2 Chip Clock Cycles ............................................................................. 4-6
Table 4-2. IP2 Chip Overall Memory Map ............................................................... 4-9
Table 4-3. IP2 Chip Memory Map - Control and Status Registers ......................... 4-11