Motorola MVME172 User Manual
Page 325
Programming Model
http://www.mcg.mot.com/literature
5-35
5
The states of RSIZ2-0 after power-up, soft, or local reset,
match those of the RSIZ2-0 bits from the reset serial bit
stream.
SELI1, SELI0
The SELI1, SELI0 control bits determine the base address
at which the control and status registers respond as shown
below:
The states of SELI1 and SELI0 after power-up, soft, or
local reset, match those of the SELI1 and SELI0 bits from
the reset serial bit stream.
FSTRD
The FSTRD control bit determines the speed at which
DRAM reads occur. When it is 1, DRAM reads happen at
full speed. When it is 0, DRAM reads are slowed by one
RSIZ2
RSIZ1
RSIZ0
DRAM Array Size
0
0
0
4MB using one 144-bit wide
block of 256Kx4 DRAMs
0
0
1
8MB using two 144-bit wide
blocks of 256Kx4 DRAMs
0
1
0
16MB using one 144-bit wide
block of 1Mx4 DRAMs
0
1
1
32MB using two 144-bit wide
blocks of 1Mx4 DRAMs
1
0
0
64MB using one 144-bit wide
block of 4Mx4 DRAMs
1
0
1
128MB using two 144-bit wide
blocks of 4Mx4 DRAMs
1
1
0
Reserved
1
1
1
Reserved
SELI1
SELI0
Register Base Address
0
0
$FFF43000
0
1
$FFF43100
1
0
$FFF43200
1
1
$FFF43300