Motorola MVME172 - Manual (Page 240)

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IP2 Chip
4
addresses are not aligned, so the local bus and the IndustryPack can
operate at their maximum data transfer sizes. The FIFO also buffers
enough data so that accesses to the local bus are in the burst mode.
Each DMAC also supports command chaining through the use of a singly-
linked list built in local (not IP) memory. Each entry in the list includes an
IP address, a local bus address, a byte count, a control word, and a pointer
to the next entry. When the command chaining mode is enabled, the
DMAC reads and executes commands from the list in local memory until
all commands are executed.
Each DMAC can be programmed to generate an interrupt request when
any specific table entry has completed, when the byte count reaches zero,
when an error condition occurs, or when the DMAEND* signal is asserted
by the IndustryPack.
The DMA arbiter has two modes of operation. One mode is to implement
a round robin type of arbitration, which guarantees equal access to the
local bus. The other method is to set the arbitration priority to one of four
states. In this case, the priority is constant with one DMA channel having
the highest priority, and the other three having the second, third, and fourth
highest priority.
Note that the IP specification supports a DMA burst where the DMA
cycles can be executed back to back. The DMA arbiter logic will not
release a DMA channel until a burst of IP cycles are completed, if the burst
protocol is observed. However, if the burst protocol is not observed, the
arbiter is released and the next DMA request/grant is resolved. This takes
two clock cycles due to the asynchronous clocks controlling the MC68060
local bus and the IP busses. The IP designer should take this into
consideration if maximum DMA bandwidth availability is required.
Note also that when the DMA register context is updated for the next
command packet, a DMA function is used. The state of the snoop control
signals for this DMA function is determined by the settings of jumper J26
(as is the state of the snoop control signals for all other DMA cycle types).
Refer to the Hardware Preparation section of your MVME172 installation
and use manual.