Motorola MVME172 - Manual (Page 258)

4-22 Computer Group Literature Center Web Site
IP2 Chip
4
SIZE23-16 A, B, C, D SIZE should be programmed to match the size
of the corresponding IndustryPack memory space. The
IP2 chip performs its IndustryPack memory sizing by
masking any bit in BASE23-BASE16 whose
corresponding SIZE23-SIZE16 bit is set. The following
table shows this. Note that only certain combinations of
the SIZE bits (those shown in the table) make sense. Any
other combination of the SIZE bits yields unpredictable
results.
ADR/SIZ $FFFBC00C through $FFFBC00F (8 bits each)
BIT 7 6 5 4 3 2 1 0
NAME($0C) a_SIZE23 a_SIZE22 a_SIZE21 a_SIZE20 a_SIZE19 a_SIZE18 a_SIZE17 a_SIZE16
NAME($0D) b_SIZE23 b_SIZE22 b_SIZE21 b_SIZE20 b_SIZE19 b_SIZE18 b_SIZE17 b_SIZE16
NAME($0E) c_SIZE23 c_SIZE22 c_SIZE21 c_SIZE20 c_SIZE19 c_SIZE18 c_SIZE17 c_SIZE16
NAME($0F) d_SIZE23 d_SIZE22 d_SIZE21 d_SIZE20 d_SIZE19 d_SIZE18 d_SIZE17 d_SIZE16
OPER R/W R/W R/W R/W R/W R/W R/W R/W
RESET 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
Size Bits Address Lines
that Are
Compared
Resulting
Memory Size 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0 A31-A16 64KB
0 0 0 0 0 0 0 1 A31-A17 128KB
0 0 0 0 0 0 1 1 A31-A18 256KB
0 0 0 0 0 1 1 1 A31-A19 512KB
0 0 0 0 1 1 1 1 A31-A20 1MB
0 0 0 1 1 1 1 1 A31-A21 2MB
0 0 1 1 1 1 1 1 A31-A22 4MB
0 1 1 1 1 1 1 1 A31-A23 8MB
1 1 1 1 1 1 1 1 A31-A24 16MB
Note that 16MB is only possible using a double size IP.