Motorola MVME172 - Manual (Page 47)

Memory Maps
http://www.mcg.mot.com/literature 1-29
1
Table 1-10. IP2 Chip Memory Map - Control and Status Registers
IP2 Chip Base Address = $FFFBC000
Register
Offset
Register
Name
Register Bit Names
D7 D6 D5 D4 D3 D2 D1 D0
$00 CHIP ID 0 0 1 0 0 0 1 1
$01 CHIP
REVISION
0 0 0 0 0 0 0 1
$02 RESERVED 0 0 0 0 0 0 0 0
$03 VECTOR BASE IV7 IV6 IV5 IV4 IV3 IV2 IV1 IV0
$04 IP_a MEM
BASE UPPER
a_BASE31 a_BASE30 a_BASE29 a_BASE28 a_BASE27 a_BASE26 a_BASE25 a_BASE24
$05 IP_a MEM
BASE LOWER
a_BASE23 a_BASE22 a_BASE21 a_BASE20 a_BASE19 a_BASE18 a_BASE17 a_BASE16
$06 IP_b MEM
BASE UPPER
b_BASE31 b_BASE30 b_BASE29 b_BASE28 b_BASE27 b_BASE26 b_BASE25 b_BASE24
$07 IP_b MEM
BASE LOWER
b_BASE23 b_BASE22 b_BASE21 b_BASE20 b_BASE19 b_BASE18 b_BASE17 b_BASE16
$08 IP_c MEM
BASE UPPER
c_BASE31 c_BASE30 c_BASE29 c_BASE28 c_BASE27 c_BASE26 c_BASE25 c_BASE24
$09 IP_c MEM
BASE LOWER
c_BASE23 c_BASE22 c_BASE21 c_BASE20 c_BASE19 c_BASE18 c_BASE17 c_BASE16
$0A IP_d MEM
BASE UPPER
d_BASE31 d_BASE30 d_BASE29 d_BASE28 d_BASE27 d_BASE26 d_BASE25 d_BASE24
$0B IP_d MEM
BASE LOWER
d_BASE23 d_BASE22 d_BASE21 d_BASE20 d_BASE19 d_BASE18 d_BASE17 d_BASE16
$0C IP_a MEM
SIZE
a_SIZE23 a_SIZE22 a_SIZE21 a_SIZE20 a_SIZE19 a_SIZE18 a_SIZE17 a_SIZE16
$0D IP_b MEM
SIZE
b_SIZE23 b_SIZE22 b_SIZE21 b_SIZE20 b_SIZE19 b_SIZE18 b_SIZE17 b_SIZE16
$0E IP_c MEM
SIZE
c_cSIZE23 c_SIZE22 c_SIZE21 c_SIZE20 c_SIZE19 c_SIZE18 c_SIZE17 c_SIZE16
$0F IP_d MEM
SIZE
d_SIZE23 d_SIZE22 d_SIZE21 d_SIZE20 d_SIZE19 d_SIZE18 d_SIZE17 d_SIZE16
$10 IP_a INT0
CONTROL
a0_PLTY a0_E/L* a0_INT a0_IEN a0_ICLR a0_IL2 a0_IL1 a0_IL0
$11 IP_a INT1
CONTROL
a1_PLTY a1_E/L* a1_INT a1_IEN a1_ICLR a1_IL2 a1_IL1 a1_IL0
$12 IP_b INT0
CONTROL
b0_PLTY b0_E/L* b0_INT b0_IEN b0_ICLR b0_IL2 b0_IL1 b0_IL0
$13 IP_b INT1
CONTROL
b1_PLTY b1_E/L* b1_INT b1_IEN b1_ICLR b1_IL2 b1_IL1 b1_IL0
$14 IP_c INT0
CONTROL
c0_PLTY c0__E/L* c0__INT c0__IEN c0__ICLR c0__IL2 c0__IL1 c0__IL0
$15 IP_c INT1
CONTROL
c1_PLTY c1__E/L* c1__INT c1__IEN c1__ICLR c1__IL2 c1__IL1 c1__IL0
$16 IP_d INT0
CONTROL
d0_PLTY d0__E/L* d0__INT d0__IEN d0__ICLR d0__IL2 d0__IL1 d0__IL0
$17 IP_d INT1
CONTROL
d1_PLTY d1__E/L* d1__INT d1__IEN d1__ICLR d1__IL2 d1__IL1 d1__IL0