Motorola MVME172 - Manual (Page 298)

5-8 Computer Group Literature Center Web Site
MCECC
5
occurs, the local bus master is notified if such interrupts are enabled in the
control register. A software bit is available to disable the read portion of
the scrub cycle.
Refresh
The MCECC pair provides refresh control for the DRAM. It performs a
single CAS-before-RAS refresh cycle to the two DRAM blocks
approximately once every 15.6
µ
s. To prevent undue noise generation, the
MCECC pair does not refresh both blocks at once, but staggers the
refreshes by one clock cycle.
Arbitration
The MCECC pair has 3 different entities that can request use of the DRAM
cycle controller: (1) the local bus master, (2) the refresher, and (3) the
scrubber.
The MCECC pair arbiter accepts requests and provides grants to the
requesting entities as follows:
Priority is (highest to lowest) refresher, local bus, and scrubber.
When no requests are pending, the arbiter defaults to providing a local bus
grant for fast response to local bus cycles.
Although the arbiter operates on a priority basis, it also performs a pseudo
round robin algorithm in order to prevent starving any of the requesting
entities.
Chip Defaults
Some jumper option kinds of parameters need to be configured in the
MCECC pair. These options include DRAM size, DRAM speed, Control
and Status Register Selection, etc. Rather than use pins (which are
extremely scarce) for each of the options, the MCECC pair is designed to
have an external PAL or other equivalent logic provide this information at
reset time, using one pin as a serial input. The information provided to this
input pin at power-up-reset or local bus reset, is called the "reset serial bit