Motorola MVME172 - Manual (Page 294)

5-4 Computer Group Literature Center Web Site
MCECC
5
When (SC1, SC0) do not indicate that snooping is inhibited, the MCECC
pair responds differently to DRAM accesses, based on whether the cycle
is a read or a write, and on the snoop wait (SWAIT) control bit.
For a read with SWAIT = 0, the MCECC pair immediately starts a read
cycle to the DRAM and latches the data from the DRAMs. It waits,
however, for MI* to be negated before it enables the data (that has been
latched) onto the local bus and asserts TA* or TEA*. If TA* or TEA* is
asserted by another local bus slave before MI* is negated, then the
MCECC pair assumes that the cycle is over and that the DRAM is not to
participate in that cycle.
For a read with SWAIT = 1, the MCECC pair behaves the same as with
SWAIT = 0 except that it does not start the DRAM read cycle until it sees
the MI* signal negated. Note that this means that if another local bus slave
asserts TA* or TEA* before MI* is negated, then the MCECC pair never
starts the DRAM read cycle.
For a write cycle, the MCECC pair always waits for MI* to be negated
before it begins a write cycle to the DRAM. If another local bus slave
asserts TA* or TEA* before MI* is negated, then the MCECC pair never
starts the DRAM write cycle.
ECC
The MCECC pair performs single bit error correction and double bit error
detection (SECDED). The 32 bit wide local data bus is divided into lower
(D00-D15) and upper (D16-D31) halves. Each half is routed through an
MCECC, which multiplexes it with half of the 128 bit wide DRAM. This
allows each MCECC to connect to 64 bits of the DRAM. Each MCECC
additionally connects to 8 bits of check bit DRAM. This actually makes the
DRAM array 144 bits wide (128 bits of normal data and 16 bits of check
data).
Cycle Types
To support ECC, the MCECC pair always deals with DRAM using full
width (144 bits, 72 bits for each MCECC) accesses. When the local bus
master requests any size read of DRAM, the MCECC pair reads 144 bits.
When the local bus master requests a line write to DRAM, the MCECC