Motorola MVME172 User Manual
Page 259
Programming Model
http://www.mcg.mot.com/literature
4-23
4
IP_a, IP_b, IP_c, and IP_d; IRQ0 and IRQ1 Interrupt Control
Registers
The registers which control IP_c and IP_d are not used on the 200/300-
Series MVME172
.
IL2-IL0
These three bits select the interrupt level for the
corresponding IndustryPack interrupt request. Level 0
does not generate an interrupt.
ICLR
In edge-sensitive mode, writing a logic 1 to this bit clears
the corresponding INT status bit. In level-sensitive mode,
this bit has no function. It always reads as 0.
IEN
When IEN is set, the interrupt is enabled. When IEN is
cleared, the interrupt is disabled.
INT
When this bit is high, an interrupt is being generated for
the corresponding IndustryPack IRQ. The interrupt is at
the level programmed in IL2-IL0.
E/L*
When this bit is high, the interrupt is edge sensitive. When
the bit is low, the interrupt is level sensitive.
ADR/SIZ
$FFFBC010 through $FFFBC017 (8 bits each)
BIT
7
6
5
4
3
2
1
0
NAME($10)
a0_PLTY
a0_E/L*
a0_INT
a0_IEN
a0_ICLR
a0_IL2
a0_IL1
a0_IL0
NAME($11)
a1_PLTY
a1_E/L*
a1_INT
a1_IEN
a1_ICLR
a1_IL2
a1_IL1
a1_IL0
NAME($12)
b0_PLTY
b0_E/L*
b0_INT
b0_IEN
b0_ICLR
b0_IL2
b0_IL1
b0_IL0
NAME($13)
b1_PLTY
b1_E/L*
b1_INT
b1_IEN
b1_ICLR
b1_IL2
b1_IL1
b1_IL0
NAME($14)
c0_PLTY
c0_E/L*
c0_INT
c0_IEN
c0_ICLR
c0_IL2
c0_IL1
c0_IL0
NAME($15)
c1_PLTY
c1_E/L*
c1_INT
c1_IEN
c1_ICLR
c1_IL2
c1_IL1
c1_IL0
NAME($16)
d0_PLTY
d0_E/L*
d0_INT
d0_IEN
d0_ICLR
d0_IL2
d0_IL1
d0_IL0
NAME($17)
d1_PLTY
d1_E/L*
d1_INT
d1_IEN
d1_ICLR
d1_IL2
d1_IL1
d1_IL0
OPER
R/W
R/W
R
R/W
C
R/W
R/W
R/W
RESET
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R