Motorola MVME172 - Manual (Page 195)

Functional Description
http://www.mcg.mot.com/literature 3-7
3
addresses for the devices are defined as follows. Note that CSR bits were
added to the General Control Register to control the delay time for the
Z85230 IACK cycle.
Tick Timers
The MC2 chip implements four 32-bit tick timers. These timers are
identical to the timers in the VMEchip2. The timers run on a 1 MHz clock
which is derived from the processor clock by a prescaler.
Each timer has a 32-bit counter, a 32-bit compare register, and a clear-on-
compare enable bit. The counter is readable and writable at any time.
These timers can be used to generate interrupts at various rates or the
counters can be read at various times for interval timing. There are two
modes of operation for these timers: free-running and clear-on-compare.
In the free-running mode, the timers have a resolution of 1
µ
s and roll over
after the count reaches the maximum value $FFFFFFFF. The terminal
count period for the timers is 71.6 minutes.
When the counter is enabled in the clear-on-compare mode, it increments
every 1
µ
s until the counter value matches the value in the compare
register. When a match occurs, the counter is cleared.
When a match occurs, in either mode, an interrupt is sent to the local bus
interrupter and the overflow counter is incremented. An interrupt to the
local bus is only generated if the tick timer interrupt is enabled by the local
bus interrupter. The overflow counter can be cleared by writing a one to
the overflow clear bit.
Address Range SCC Device Number
$FFF45000 - $FFF453FF 0
$FFF45400 - $FFF457FF 1
$FFF45800 - $FFF45BFF 2
$FFF45C00 - $FFF45FFF 3