Motorola MVME172 - Manual (Page 288)

4-52 Computer Group Literature Center Web Site
IP2 Chip
4
IP to Local Bus Data Routing
This section shows data routing from an IP to the local bus.
Memory Space Accesses
The following table shows the data routing when accessing IP memory
space.
IPWIDTH refers to the memory space width that has been programmed
into the general control register for the IndustryPack being accessed.
LBSIZE refers to local bus transfer size.
LBA refers to local bus address signals 1 and 0.
LD refers to the local data bus.
IPA refers to IndustryPack address signals 2,1,0. The IP2 chip implements
dynamic bus sizing for memory space accesses whose local bus size is
greater than the port width of the IndustryPack that is being accessed.
Because of this, the IP2 chip performs 1, 2 or 4 IP memory space cycles
for each local bus cycle. The IPA column in the table lists 1, 2, or 4
addresses to indicate the address for each IP cycle that is performed.
IPXD refers to the IP_a data bus (IPAD) when accessing IP_a or IP_c. It
refers to the IP_b data bus (IPBD) when accessing IP_b or IP_d.