Motorola MVME172 - Manual (Page 229)

Programming Model
http://www.mcg.mot.com/literature 3-41
3
ABORT Switch Interrupt Control Register
The following table describes the ABORT switch interrupt logic in the
MC2 chip.
IL2-IL0 These three bits select the interrupt level for the ABORT
switch. Level 0 does not generate an interrupt.
ICLR Writing a logic 1 to this bit clears the abort interrupt (i.e.,
the INT bit in this register). This bit is always read as zero.
IEN When this bit set high, the interrupt is enabled. The
interrupt is disabled when this bit is low.
INT When this bit is high, an interrupt is being generated for
the ABORT switch. Therefore the interrupt is level-
sensitive to the presence of the INT bit. The interrupt is at
the level programmed in IL2-IL0.
ABS The ABORT switch status set to a one indicates that the
ABORT switch is pressed. When it is a zero, the switch is
inactive.
ADR/SIZ $FFF42040 (8 bits)
BIT 7 6 5 4 3 2 1 0
NAME ABS INT IEN ICLR IL2 IL1 IL0
OPER R R R R/W C R/W R/W R/W
RESET 0 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL