Motorola MVME172 - Manual (Page 223)

Programming Model
http://www.mcg.mot.com/literature 3-35
3
MVME172 Version Register
The contents of a PAL and the state of an 8-position jumper block are
translated to bit settings of the General Purpose Inputs Register, Version
Register and DRAM/SRAM Options Register when the MC2 chip is reset.
These registers are read only. Writes to these registers are terminated
without exception but do not change their contents.
V0 V0 and V4 indicated the speed of the processor and local
bus. Refer to the following table for the bit definitions.
** No plans to productize this combination.
V1 V1 set to a one indicates that the VMEchip2 ASIC is not
present. V1 set to a zero indicates that a VMEbus interface
is present.
If V1 = 0, the MC2 chip reset logic and local bus access
timer are inhibited.
V2 V2 set to a one indicates that the SCSI interface is not
present. V2 set to a zero indicates that a SCSI interface is
present.
ADR/SIZ $FFF4202C (8 bits)
BIT 15 14 - 9 8
NAME V7 V6 - V1 V0
OPER R R R
RESET Application Specific
V0 V4
Processor Type
Processor/Bus
Frequency
0 MC68LC060 50/25 **
0 MC68060 50/25 **
1 0 MC68LC060 64/32
1 1 MC68060 60/30