Motorola MVME172 - Manual (Page 143)

LCSR Programming Model
http://www.mcg.mot.com/literature 2-65
2
DLOB When this bit is set, the DMAC received a TEA and the
status indicated off-board. This bit is cleared when the
DMAC is enabled.
DLPE When this bit is set, the DMAC received a TEA and the
status indicated a parity error during a DRAM data
transfer. This bit is cleared when the DMAC is enabled.
This bit is not defined for MVME172 implementation.
DLBE When this bit is set, the DMAC received a TEA and
additional status was not provided. This bit is cleared
when the DMAC is enabled.
MLTO When this bit is set, the MPU received a TEA and the
status indicated a local bus time-out. This bit is cleared by
a writing a one to the MCLR bit in this register.
Programming the Tick and Watchdog Timers
The VMEchip2 has two 32-bit tick timers and one watchdog timer. This
section provides addresses and bit level descriptions of the prescaler, tick
timer, watchdog timer registers and various other timer registers.
VMEbus Arbiter Time-out Control Register
This register controls the VMEbus arbiter time-out timer.
ARBTO When this bit is high, the VMEbus grant time-out timer is
enabled. When this bit is low, the VMEbus grant timer is
disabled. When the timer is enabled and the arbiter does
not receive a BBSY signal within 256
µ
s after a grant is
issued, the arbiter asserts BBSY and removes the grant.
The arbiter then rearbitrates any pending requests.
ADR/SIZ $FFF4004C (8 bits [1 used] of 32)
BIT 31 30 29 28 27 26 25 24
NAME ARBTO
OPER R/W
RESET 0 PS