Motorola MVME172 - Manual (Page 256)

4-20 Computer Group Literature Center Web Site
IP2 Chip
4
Note Note that the Memory Bases for any of IP_a, IP_b, IP_c,
IP_d, that are enabled, should not be programmed to overlap
each other.
IP_a or Double Size IP_ab Memory Base Address Registers
IP_b Memory Base Address Registers
ADR/SIZ $FFFBC004 and $FFFBC005 (8 bits each)
BIT 7 6 5 4 3 2 1 0
NAME($04) a_BASE31 a_BASE30 a_BASE29 a_BASE28 a_BASE27 a_BASE26 a_BASE25 a_BASE24
NAME($05) a_BASE23 a_BASE22 a_BASE21 a_BASE20 a_BASE19 a_BASE18 a_BASE17 a_BASE16
OPER R/W R/W R/W R/W R/W R/W R/W R/W
RESET 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
ADR/SIZ $FFFBC006 and $FFFBC007 (8 bits each)
BIT 7 6 5 4 3 2 1 0
NAME($06) b_BASE31 b_BASE30 b_BASE29 b_BASE28 b_BASE27 b_BASE26 b_BASE25 b_BASE24
NAME($07) b_BASE23 b_BASE22 b_BASE21 b_BASE20 b_BASE19 b_BASE18 b_BASE17 b_BASE16
OPER R/W R/W R/W R/W R/W R/W R/W R/W
RESET 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R