Motorola MVME172 - Manual (Page 75)

Software Support Considerations
http://www.mcg.mot.com/literature 1-57
1
MPU Notification:
53C710 Interrupt.
Status:
53C710 DMA Status Register 53C710 DMA Interrupt Status Register
MC2 chip SCSI Error Status Register ($FFF4202C).
Comments:
53C710 interrupt enables are controlled in the 53C710 and in the MC2
chip SCSI Interrupt Control Register ($FFF4202F).
Example of the Proper Use of Bus Timers
In this example, the use of the bus timers is illustrated by describing the
sequence of events when the MPU on one MVME172 accesses the local
bus memory on another MVME172 using the VMEbus. In this scenario
there are three bus timers involved. These are the local bus timer, the
VMEbus access timer, and the Global VMEbus timer. The local bus timer
measures the time an access to an onboard resource takes. The VMEbus
timer measures the time from when the VMEbus request has been initiated
to when a VMEbus grant has been obtained. The global bus timer
measures the time from when a VMEbus cycle begins to when it
completes. Normally these timers should be set to quite different values.
An example of one MVME172 accessing another MVME172 illustrates
the use of these timers.
When the processor or another local bus master initiates an access to the
VMEbus, it first waits until any other local bus masters get off the local
bus. Then it begins its cycle and the local bus timer starts counting. It
continues to count until an address decode of the VMEbus address space
is detected and then terminates. This is normally a very short period of
time. In fact all local bus non-error bus accesses are normally very short,
such as the time to access onboard memory. Therefore, it is recommended
this timer be set to a small value, such as 256
µ
sec.
The next timer to take over when one MVME172 accesses another is the
VMEbus access timer. This measures the time between when the VMEbus
has been address decoded and hence a VMEbus request has been made,