Motorola MVME172 - Manual (Page 89)

Functional Blocks
http://www.mcg.mot.com/literature 2-11
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Using control register bits in the LCSR, the DMAC can be configured to
provide the following VMEbus capabilities:
Addressing capabilities: A16, A24, A32
Data transfer capabilities: D16, D32, D16/BLT, D32/BLT,
D64/BLT (BLT = block transfer)
Using the DMA AM control register, the address modifier code that the
VMEbus DMA controller places on the VMEbus can be programmed
under software control. In addition, the DMAC can be programmed to
execute block-transfer cycles over the VMEbus.
Complying with the VMEbus specification, the DMAC automatically
terminates block-transfer cycles whenever a 256-byte (D32/BLT) or 2-KB
(D64/BLT) boundary is crossed. It does so by momentarily releasing AS
and then, in accordance with its bus release/bus request configuration,
initiating a new block-transfer cycle.
To optimize VMEbus use, the DMAC automatically adjusts the size of
individual data transfers until 64-bit transfers (D64/BLT mode), 32-bit
transfers (D32 mode) or 16-bit transfers (D16 mode) can be executed.
Based on the address of the first byte, the DMAC transfers single-byte,
double-byte, or a mixture of both, and then continues to execute transfer
cycles based on the programmed data width. Based on the address of the
last byte, the DMAC transfers single-byte, double-byte, or a mixture of
both to end the transfer.
To optimize local bus use when the VMEbus is operating in the D16 mode,
the data FIFO converts D16 VMEbus transfers to D32 local bus transfers.
The FIFO also aligns data if the source and destination addresses are not
aligned so the local bus and VMEbus can operate at their maximum data
transfer sizes.
To allow other boards access to the VMEbus, the DMAC has bus tenure
timers to limit the time the DMAC spends on the VMEbus and to ensure a
minimum time off the VMEbus. Since the local bus is generally faster than
the VMEbus, other local bus masters may use the local bus while the
DMAC is waiting for the VMEbus.