Motorola MVME2300 Series - Manual (Page 10)

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Nesting of Interrupt Events ....................................................................... 2-62
Spurious Vector Generation ...................................................................... 2-62
Interprocessor Interrupts (IPI)................................................................... 2-62
8259 Compatibility.................................................................................... 2-62
Raven-Detected Errors .............................................................................. 2-63
Timers ....................................................................................................... 2-63
Interrupt Delivery Modes .......................................................................... 2-64
Block Diagram Description.............................................................................. 2-65
Program-Visible Registers ........................................................................ 2-66
Interrupt Pending Register (IPR) .............................................................. 2-66
Interrupt Selector (IS) ............................................................................... 2-66
Interrupt Request Register (IRR) .............................................................. 2-67
In-Service Register (ISR) .......................................................................... 2-67
Interrupt Router ......................................................................................... 2-67
MPIC Registers ................................................................................................ 2-69
RavenMPIC Registers ............................................................................... 2-69
Feature Reporting Register ....................................................................... 2-73
Global Configuration Register .................................................................. 2-74
Vendor Identification Register .................................................................. 2-75
Processor Init Register .............................................................................. 2-75
IPI Vector/Priority Registers..................................................................... 2-76
Spurious Vector Register .......................................................................... 2-77
Timer Frequency Register......................................................................... 2-77
Timer Current Count Registers ................................................................. 2-78
Timer Base Count Registers...................................................................... 2-78
Timer Vector/Priority Registers ................................................................ 2-79
Timer Destination Registers...................................................................... 2-80
External Source Vector/Priority Registers ................................................ 2-81
External Source Destination Registers ...................................................... 2-82
Raven-Detected Errors Vector/Priority Register ...................................... 2-83
Raven-Detected Errors Destination Register ............................................ 2-84
Interprocessor Interrupt Dispatch Registers.............................................. 2-84
Interrupt Task Priority Registers ............................................................... 2-85
Interrupt Acknowledge Registers.............................................................. 2-86
End-of-Interrupt Registers ........................................................................ 2-86
Programming Notes.......................................................................................... 2-87
External Interrupt Service ......................................................................... 2-87
Reset State ................................................................................................. 2-88
Interprocessor Interrupts ........................................................................... 2-89
Dynamically Changing I/O Interrupt Configuration................................. 2-89
EOI Register.............................................................................................. 2-90
Interrupt Acknowledge Register ............................................................... 2-90