Motorola MVME2300 Series - Manual (Page 99)

Functional Description
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When any bit in the MPC Error Status register is set, the Raven ASIC will
attempt to latch as much information as possible about the error in the
MPC Error Address and Attribute registers. Information is saved as
follows:
Each MERST error bit may be programmed to generate a machine check
and/or a standard interrupt. The error response is programmed through the
MPC Error Enable register on a source-by-source basis. When a machine
check is enabled, either the MID field in the MPC Error Attribute register
or the DFLT bit in the MEREN register determine the master to which the
machine check is directed. For errors in which the master that originated
the transaction can be determined, the MID field is used, provided the MID
is%00 (processor 0), %01 (processor 1), or %10 (processor 2). For errors
not associated with a particular MPC master, or associated with masters
other than processor 0, 1, or 2, the DFLT bit is used. One example of an
error condition which cannot be associated with a particular MPC master
would be a PCI system error.
Transaction Ordering
The Raven ASIC supports transaction ordering with an optional FIFO
flushing option. The FLBRD (Flush Before Read) bit within the GCSR
register controls the flushing of PCI write-posted data when performing
MPC-originated read transactions.
Error Status
Error Address
and Attributes
MATO From MPC bus
SMA From PCI bus
RTA From PCI bus
PERR Invalid
SERR Invalid