Motorola MVME2300 Series - Manual (Page 89)

Functional Description
http://www.motorola.com/computer/literature 2-19
2
Addressing
The PCI master will generate all memory transactions using the linear
incrementing addressing mode.
Combining, Merging, and Collapsing
The PCI master does not participate in any of these protocols.
Master Initiated Termination
The PCI master can handle any defined method of target retry, target
disconnect, or target abort. If the target responds with a retry, the PCI
master will wait for the required two clock periods and attempt the
transaction again. The attempts will continue indefinitely until the
transaction either completes, or is aborted by the target, or is aborted due
to a Raven-detected bridge lock. The same happens if the target responds
with a disconnect and there is still data to be transferred.
If the PCI master detects a target abort during a read, any untransferred
read data will be filled with 1s. If the PCI master detects a target abort
during a write, any untransferred portions of data will be dropped. The
same rule applies if the PCI master generates a Master Abort cycle.
-- Unsupported -- 1000 Reserved
-- Unsupported -- 1001 Reserved
CONADD/CONDAT Read x x 1010 Configuration Read
CONADD/CONDAT Write x x 1011 Configuration Write
-- Unsupported -- 1100 Memory Read Multiple
-- Unsupported -- 1101 Dual Address Cycle
MPC Mapped PCI Space Read 0 1 1110 Memory Read Line
-- Unsupported -- 1111 Memory Write and
Invalidate
Table 2-5. PCI Master Command Codes (Continued)
Entity Addressed
MPC
Transfer Type
TBST
∗
MEM C/BE PCI Command