Motorola MVME2300 Series User Manual
Page 277
IN-3
I
N
D
E
X
reading internal CSRs
software considerations
Falcon-controlled system registers
false, definition of
fast refresh control bit (Falcon chip set)
Feature Reporting register (RavenMPIC)
features
Falcon ECC Memory Controller chip set
MVME2300 series boards
Raven PCI Bridge ASIC
Flash (see ROM/Flash interface)
functional description
Falcon ECC Memory Controller chip set
Raven PCI Bridge ASIC
G
General Control/Status and Feature registers
General-Purpose registers
general-purpose software-readable header
(J10/J17)
generating PCI cycles (Raven PCI Bridge
Global Configuration register (RavenMPIC)
H
half-word, definition of
headers
J10/J17 (general-purpose software-read-
able header)
hexadecimal character, symbol for
hints for programming
I
I/O Base register
Interprocessor Interrupt Dispatch registers
(Raven MPIC)
interprocessor interrupts
Interrupt Acknowledge registers (Raven
interrupt delivery modes (Raven ASIC)
Interrupt Enable control bits (Falcon chip set)
interrupt handling, MVME2300 boards
Interrupt Pending register (IPR)
Interrupt Request register (IRR)
interrupt router (Raven ASIC)
interrupt selector (IS)
Interrupt Task Priority registers (Raven-
interrupter and interrupt handler (Universe
IPI Vector/Priority registers (Raven MPIC)
ISA local resource bus
J
jumper headers
J10/J17 (general-purpose software-read-
able header)
L
Large Scale Integration (LSI)
LM/SIG Control register
Location Monitor
Lower Base Address register
Upper Base Address register
M
manual terminology
manufacturers’ documents