Motorola MVME2300 Series - Manual (Page 84)

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Raven PCI Bridge ASIC
2
PCI Slave
The PCI slave provides the control logic needed to interface the PCI bus to
the Raven’s FIFO buffers. The PCI slave can accept either 32-bit or 64-bit
transactions, but it can accept only 32-bit addressing.
There is no limit to the length of the transfer that the slave can handle.
During posted write cycles, the slave will continue to accept write data
until the write-post FIFO is full. If the write-post FIFO is full, the slave will
hold off the master with wait states until there is more room in the FIFO.
The slave will not initiate a disconnect.
If the write transaction is compelled, the slave will hold off the master with
wait states while each beat of data is being transferred. The slave will
acknowledge the completion of the transfer only after the data transfer has
successfully completed on the MPC bus.
If a read transaction is occurring within an address space marked for
prefetching, the slave (in conjunction with the MPC master) will attempt
to read far enough ahead on the MPC bus to allow for an uninterrupted
burst transaction on the PCI bus. Read transactions within address spaces
marked for no prefetching will be acknowledged on the PCI bus only after
a single beat read has successfully completed on the MPC bus.
Each read on the MPC bus will begin only after the previous read has been
acknowledged on the PCI bus and there is an indication that the PCI master
wishes more data to be transferred.
The following paragraphs identify some associations between the
operation of the PCI slave and the requirements of the PCI 2.0 Local Bus
Specification.