Motorola MVME2300 Series - Manual (Page 249)

Interrupt Handling
http://www.motorola.com/computer/literature 5-5
5
interrupt can be routed to the same ISA IRQ line. The PIB can be
programmed to handle the PCI interrupts if the RavenMPIC is either not
present or not used.
The following figure shows the interrupt structure of the PIB.
Figure 5-2. PIB Interrupt Handler Block Diagram
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IRQx
PIRQ Route
Control Register
PIRQ Route
Control Register
PIRQ Route
Control Register
PIRQ Route
Control Register
PIRQ3_
IRQx PIRQ2_
IRQx PIRQ1_
IRQx PIRQ0_
Controller 2
(INT2)
IRQ8
IRQ9
IRQ11
IRQ10
IRQ12
IRQ13
IRQ14
IRQ15
0
1
2
3
4
5
6
7
Controller 1
(INT1)
Timer1/Counter0
IRQ1
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
0
1
2
3
4
5
6
7
INTR