Motorola MVME2300 Series - Manual (Page 74)

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Raven PCI Bridge ASIC
2
Functional Description
The Raven data path logic is subdivided into the following functions:
❏ Data Path ‘A’ FIFOs/muxes
❏ Data Path ‘B’ FIFOs/muxes
❏ PCIADIN, MPCADIN, Mux PCI, and Mux MPC
Address decoding is handled in the PCI Decode and MPC Decode blocks.
The control register logic is contained in the PCI Registers and MPC
Registers blocks. The interrupt controller (RavenMPIC) and the MPC
arbiter functions make up the remainder of the Raven design.
The data path function imposes some restrictions on access to the
RavenMPIC, the PCI registers, and the MPC registers. The RavenMPIC
and the PCI registers are only accessible to PCI-originated transactions.
The MPC registers are only accessible to MPC-originated transactions.
MPC Bus Interface
The MPC Bus interface is designed to be coupled directly to up to two
MPC603 or MPC604 microprocessors as well as a memory/cache
subsystem. It uses a subset of the capabilities of the MPC60x bus protocol.
MPC Address Mapping
The Raven will map either PCI memory space or PCI I/O space into MPC
address space using four programmable map decoders. These decoders
provide windows into the PCI bus from the MPC bus. The most significant
16 bits of the MPC address are compared with the address range of each
map decoder, and if the address falls within the specified range, the access
is passed on to PCI. An example of this appears in
Figure 2-2 .