Motorola MVME2300 Series - Manual (Page 87)

Functional Description
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Parity
The PCI slave supports address parity error detection, data parity
generation and data parity error detection.
Cache Support
The PCI slave does not participate in the PCI caching protocol.
PCI Write Posting
If write-posting is enabled, the Raven stores the target address, attributes,
and up to 128 bytes of data from one PCI write transaction and
immediately acknowledges the transaction on the PCI bus. This allows the
slower PCI to continue to transfer data at its maximum bandwidth, and the
faster MPC bus to accept data in high-performance cache-line burst
transfers.
Only one PCI transaction may be write-posted at any given time. If the
Raven is busy processing a previous write-posted transaction when a new
PCI transaction begins, the next PCI transaction is delayed (TRDY
∗
is not
asserted) until the previous transaction has completed. If during a
transaction the write-post buffer is filled, subsequent PCI data transfers are
delayed (TRDY
∗
is not asserted) until the Raven has removed some data
from the FIFO. Under normal conditions, the Raven should be able to
empty the FIFO faster than the PCI bus can fill it.
PCI Configuration cycles intended for internal Raven registers are also
delayed if the Raven is busy, so that control bits which may affect write-
posting do not change until all write-posted transactions have completed.
PCI Master
The PCI master, in conjunction with the capabilities of the MPC slave, will
attempt to move data in either single-beat or four-beat (burst) transactions.
All single-beat transactions will be subdivided into one or two 32-bit
transfers, depending on the alignment and size of the transaction. The PCI
master will attempt to transfer all four-beat transactions in 64-bit mode if
the PCI bus has 64-bit mode enabled. If at any time during the transaction
the PCI target indicates that it cannot support 64-bit mode, the PCI master
will continue to transfer the remaining data in 32-bit mode.