Raven-detected errors destination register, Interprocessor interrupt dispatch registers – Motorola MVME2300 Series User Manual
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Raven PCI Bridge ASIC
2
Raven-Detected Errors Destination Register
This register indicates the possible destinations for the Raven-detected
error interrupt source. These interrupts operate in the Distributed interrupt
delivery mode.
P1
Processor 1. The interrupt is pointed to processor 1.
P0
Processor 0. The interrupt is pointed to processor 0.
Interprocessor Interrupt Dispatch Registers
There are four Interprocessor Interrupt Dispatch registers. Writing to an
IPI Dispatch register with the P0 and/or P1 bit set causes an interprocessor
interrupt request to be sent to one or more processors. Note that each IPI
Offset
$10210
Bit
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0 9 8 7 6 5 4 3 2 1 0
Name
RAVEN DETECTED ERROR DESTINATION
P1
P0
Operation
R
R
R
R
R/W
R/W
Reset
$00
$00
$00
$00
0
0
Offset
Processor 0 $20040, $20050, $20060, $20070
Processor 1 $21040, $21050,$21060, $21070
Bit
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0 9 8 7 6 5 4 3 2 1 0
Name
IPI DISPATCH
P1
P0
Operation
R
R
R
R
R/
W
R/
W
Reset
$00
$00
$00
$00
0
0