Motorola MVME2300 Series - Manual (Page 88)

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The PCI master can support Critical Word First (CWF) burst transfers. The
PCI master will divide this transaction into two parts. The first part will
start on the address presented with the CWF transfer request and continue
up to the end of the current cache line. The second transfer will start at the
beginning of the associated cache line and work its way up to (but not
including) the word addressed by the CWF request.
It should be noted that even though the master can support burst
transactions, a majority of the transaction types handled are single-beat
transfers. Since PCI space is typically not configured as cacheable, burst
transactions to PCI space would not naturally occur. Burst transactions
must be supported, however, since it is conceivable that bursting could
happen. For example, nothing prevents the processor from loading up a
cache line with PCI write data and manually flushing the cache line.
The following paragraphs identify some associations between the
operation of the PCI master and the requirements of the PCI 2.0 Local Bus
Specification.
Command Types
The PCI command codes generated by the PCI master depend on the type
of transaction being performed on the MPC bus. Please refer to the MPC
Slave section earlier in this chapter for a further description of MPC bus
read and MPC bus write transactions.
Table 2-5 summarizes the command
types supported and shows how they are generated.
Table 2-5. PCI Master Command Codes
Entity Addressed
MPC
Transfer Type
TBST
∗
MEM C/BE PCI Command
PIACK Read x x 0000 Interrupt Acknowledge
CONADD/CONDAT Write x x 0001 Special Cycle
MPC Mapped PCI Space Read x 0 0010 I/O Read
Write x 0 0011 I/O Write
-- Unsupported -- 0100 Reserved
-- Unsupported -- 0101 Reserved
MPC Mapped PCI Space Read 1 1 0110 Memory Read
Write x 1 0111 Memory Write