Table 3-4 – Motorola MVME2300 Series User Manual
Page 171
Functional Description
http://www.motorola.com/computer/literature
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Table 3-4. PowerPC Bus to DRAM Access Timing — 50ns Hyper Devices
Notes
1. These numbers assume that the PowerPC 60x bus master is doing
address pipelining with TS_ occurring at the minimum time after
AACK_ is asserted. Also, the two numbers shown in the 1st Beat
column are for page miss/page hit.
2. In some cases, the numbers shown are averages and specific
instances may be longer or shorter.
Access Type
Clock Periods Required For:
Total
Clocks
1st
Beat
2nd
Beat
3rd
Beat
4th
Beat
4-Beat Read after Idle (Quad-
word aligned)
8
1
1
1
11
4-Beat Read after Idle (Quad-
word misaligned)
8
2
1
1
12
4-Beat Read after 4-Beat Read
(Quad-word aligned)
5/2
1
1 1
1
8/5
4-Beat Read after 4-Beat Read
(misaligned)
4/2
1
2
1
1
8/6
4-Beat Write after Idle
4
1
1
1
7
4-Beat Write after 4-Beat Write
(Quad-word aligned)
4/3
1
1
1
1
7/6
1-Beat Read after Idle
8
-
-
-
8
1-Beat Read after 1-Beat Read
7/5
1
-
-
-
7/5
1-Beat Write after Idle
4
-
-
-
4
1-Beat Write after 1-Beat Write
9/7
1
-
-
-
9/7