Motorola MVME2300 Series - Manual (Page 134)

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Interrupt Delivery Modes
The direct and distributed interrupt delivery modes are supported. Note
that the direct delivery mode has sub modes of multicast or non-multicast.
The Interprocessor Interrupts (IPIs) and Timer interrupts operate in the
direct delivery mode. The externally sourced or I/O interrupts operate in
the distributed mode.
In direct delivery mode, the interrupt is directed to one or both processors.
If it is directed to two processors (i.e. multicast), it will be delivered to two
processors. The interrupt is delivered to the processor when the priority of
the interrupt is greater than the priority contained in the task register for
that processor, and when the priority of the interrupt is greater than any
interrupt which is in-service for that processor. An interrupt is considered
to be in service from the time its vector is returned during an interrupt
acknowledge cycle until an EOI is received for that interrupt. The EOI
cycle indicates the end of processing for the highest-priority in-service
interrupt.
In distributed delivery mode, the interrupt is pointed to one or more
processors but it will be delivered to only one processor. Therefore, for
externally sourced or I/O interrupts, multicast delivery is not
supported.The interrupt is delivered to a processor when the priority of the
interrupt is greater than the priority contained in the task register for that
processor, and when the priority of the interrupt is greater than any
interrupt which is in-service for that processor, and when the priority of
that interrupt is the highest of all interrupts pending for that processor, and
when that interrupt is not in-service for the other processor. If both
destination bits are set for each processor, the interrupt will be delivered to
the processor that has a lower task register priority.
Note Because a deadlock condition can occur when the task register
priorities for each processor are the same and both processors are
targeted for interrupt delivery, the interrupt will be delivered to
processor 0.